SATH: Simulated Annealing C code To FPGA Hardware compiler

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Beschreibung

A tool flow is presented for deriving accelerator circuits on an FPGA from ANSI C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based scheduling software used for spacecraft systems is explained. The goal of the tool is the derivation of a design that maximizes throughput while minimizing footprint. Results obtained are compared with a peer C to RTL tool, a space-borne embedded processor and a commodity desktop processor for a variety of problems.

Autorentext

Dr. Jonathan Phillips received his B.S. (Brigham YoungUniversity, 2000), his M.S. and Ph.D. in Electrical Engineering (Utah State University, 2004 and2008). He is currently employed at the USU Research Foundation, where he continues toinvestigate real-world applications for multi-FPGA data processing andcommunications systems.



Klappentext

A tool flow is presented for deriving acceleratorcircuits on an FPGA from ANSI C source code by exploring architecturesolutions that conform to a preset template through scheduling andmapping algorithms. A case study carried out on simulatedannealing-based scheduling software used for spacecraft systems isexplained. The goal of the tool is the derivation of a design thatmaximizes throughput while minimizing footprint. Results obtained arecompared with a peer C to RTL tool, a space-borne embedded processor and acommoditydesktop processor for a variety of problems.

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Produktinformationen

Titel
SATH: Simulated Annealing C code To FPGA Hardware compiler
Untertitel
Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
Autor
EAN
9783639165128
ISBN
978-3-639-16512-8
Format
Kartonierter Einband
Genre
Technik
Anzahl Seiten
132
Gewicht
213g
Größe
H220mm x B150mm x T8mm
Jahr
2009
Untertitel
Englisch
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